Powertech’s $400M panel fab is where Broadcom’s ASIC volume goes when CoWoS is full
The report is right and the timing is the point: Taiwan’s Investment Commission cleared the US$400M investment on 28 October, which turns a July announcement into money that can be spent. Panel-level packaging is the second queue for AI packages, and Powertech is one of the few OSATs with custom-ASIC volume already reported booked on it. If you are modelling Broadcom’s AI revenue, this line matters more than another CoWoS wafer forecast.
Taiwan’s Powertech is reportedly partnering with Broadcom to build a $400 million panel-level packaging (PLP) fab in Singapore. @jukan05 on X
What was actually approved
The Investment Commission approved Powertech’s US$400M (about NT$12.8 billion) investment for a 30% stake in XCIP Technologies Pte Ltd, a Singapore joint venture with Broadcom, with capital injected in stages. The JV itself was announced on 16 July (@semivision_tw, @Focus_Taiwan). It is a packaging and test venture for large AI parts, and @dnystedt noted at the time that Powertech had already developed FOPLP for large AI chips and counted AMD as a client, which makes this an expansion of a qualified process rather than a green-field science project.
Why panels, in one paragraph of arithmetic
A 300 mm wafer carries about 70,700 mm² of area; Powertech’s FOPLP panel is 510 x 515 mm, about 262,700 mm², roughly 3.7x. For a package that is a large fraction of reticle size plus eight or twelve HBM stacks, the round wafer wastes the corners and the panel does not. An August write-up of the programme had capacity going from about 1,000 panels a month in 2026 to 2,000 by mid-2027 and 5,000 in 2028, with mass production from mid-2027 and the platform’s total investment reported at NT$70 billion (@HyperTechInvest, 28 Aug 2026). Those are reported numbers carried from company briefings, not filings.
The queue it serves
CoWoS capacity is fully booked, and the overflow is already visible: back-end orders are spilling over to Intel’s Malaysia operations for shared customers, with substrate suppliers being pulled in to support EMIB-T, while TSMC’s 5.5x-reticle CoWoS runs above 98% yield (@TradexWhisperer; @SemiconductorsX). When the bottleneck is the package and not the die, a second source does not need to be as good as TSMC; it needs to exist, and be qualified before the ASIC tape-out moves.
Booked before it ships
Two claims, both from the OSAT side, define the next two years: AMD and Broadcom have reportedly booked most of Powertech’s planned FOPLP capacity, with mass production from mid-2027 (@HyperTechInvest), and Powertech’s panel capacity is being watched as a hard constraint on AMD’s supply (@zephyr_z9). That is the strategic logic in one sentence: an ASIC vendor cannot outbid NVIDIA for interposer slots, so it buys a different process and a different building.
Singapore is not incidental either. It puts packaging capacity outside Taiwan, close to Broadcom’s Asian design and test footprint, and on the same island as other advanced-packaging investment — the same logic that put Micron’s HBM assembly and GlobalFoundries’ Singapore expansion there.
The catch is yield, and it is not small
Panel-level fan-out has been a decade-long promise because large panels warp, and nobody in this chain has published a qualified high-volume yield at 510 x 515 mm. Powertech’s own claim is above 90% with a 95–99% target, which is a big claim to make at that panel size. If it holds, PLP becomes the cheaper lane for ASICs and a price umbrella under CoWoS. If it slips a year, Broadcom’s ASIC ramp slips with it, because there is no third option at that volume.
What to watch
Three signposts, in order: Powertech’s monthly panel count crossing 2,000 in mid-2027 as promised; a named customer beyond AMD and Broadcom; and whether the JV’s Singapore line takes assembly only or final test as well. Test is where yield data becomes public, and yield data is what tells you whether the second queue is real.
What we could not verify
Broadcom has not confirmed the JV’s customer allocation publicly, the $400M is Powertech’s stake rather than the venture’s total cost, and the capacity and yield figures come from company statements relayed through X rather than filings. Neither company has published a panel-per-month schedule.
Sources
- @jukan05, 29 Oct 2026 04:05 UTC — Powertech/Broadcom $400M PLP fab in Singapore
- UDN — the report Jukan cites
- UDN — Investment Commission approval, 28 Oct 2026 (US$400M, 30% of XCIP Technologies)
- @semivision_tw — 16 July 2026 JV announcement, NT$12.8B
- @Focus_Taiwan — joint venture for advanced panel-level assembly
- @dnystedt, 17 Jul 2026 — Broadcom/Powertech $400M substrates JV; FOPLP for large AI chips; AMD a client
- @HyperTechInvest, 28 Aug 2026 — capacity booked by AMD and Broadcom; 1,000/2,000/5,000 panels per month; NT$70B platform; PiFO yields
- @zephyr_z9, 4 Oct 2026 — Powertech’s FOPLP capacity as a constraint on AMD
- @TradexWhisperer, 19 Aug 2026 — CoWoS fully booked, spillover to Intel Malaysia, EMIB-T substrates, 98% yields
- @SemiconductorsX, 11 Aug 2026 — 5.5x-reticle CoWoS in high-volume production, yields above 98%
FAQ
Is this a CoWoS competitor?
Partly. It competes for the same AI packages at lower interconnect density; it does not replace silicon-interposer CoWoS for the largest parts.
Why is Broadcom involved rather than just buying capacity?
Custom ASIC customers need packaging co-designed with the die. A 30% stake buys influence over the roadmap, not just a queue position.
Does this help NVIDIA?
Indirectly. Every large ASIC package that moves to a panel frees interposer and CoWoS capacity for GPU demand.
What is the risk to the thesis?
Panel warpage and yield at 510 x 515 mm. A line yielding half its panels is not a supply source; one yielding above 90% is.
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